Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency (Lecture, 3) 1st Edition

Workload charectarization and benchmarks are 2 critical components influencing computer system design, as well as processor design. This concise book focuses on the Workload charecterization issues (Throughput sensitive and Latency sensitive workloads), and how they affect processor design. You might have to look up the various benchmarks referred to in this book. At least I had to, as I am not in the business of designing computer systems or processors.Chapter 1 makes the case of CMT (chip multi-threading architecture). Chapter 2 covers Application workloads may already come with a good degree of threading already exists, and how CMT architecture exploits this property. Chapter 3 covers other considerations where legacy code with little or no direct threading can still exploit the CMT benefits via automatic Thread Level Parallelism from sequential code. It also covers recent techniques where you can get completely automated parallelization of java code. Chapter 4 covers manual programming techniques for exploiting CMT.For non-practitioner(s) of computer system design or processor design, this concise book definitely helps. Anyone with EE background (curiosity can make up for this too!) to get up to speed with recent trends in processor design. This is important because sooner or later, you will deal with computer systems using these innovations.

Un cours magistral de grande qualité sur les "multi-core micropressors".N'y cherchez pas de code d'exemple sur l'implémentation sur FPGA ou CPLD.Juste un bon cours.